FIG. 1 shows a simplified cross section of a configuration of a trench MOS. Disposed on a highly n+-doped silicon substrate 1 is an n-doped silicon layer 2 (epitaxial layer), into which a multiplicity of trenches 3 is introduced, only one trench being shown exemplarily in FIG. 1. Disposed at the side walls and at the bottom of the trenches in each case is a thin dielectric layer 4, mostly made of silicon dioxide. The inside of the trenches is filled with a conductive material 5, for example, doped polysilicon. Disposed between the trenches is a p-doped layer (p-well) 6. Highly n+-doped regions 8 (source) and highly p+-doped regions 7 (for connecting the p-well) are introduced into this p-doped layer at the surface. The surface of the entire structure is covered with a conductive layer 9, for example, with aluminum, which forms an ohmic contact with the p+-, respectively n+-doped layers 7 and 8. A thick dielectric layer 10, for example, a CVD oxide layer, insulates the conductive polysilicon layer 5 from metallization 9. Polysilicon layers 5 are galvanically connected to one another and to a metallic gate contact (not drawn). To this end, dielectric layer 10 and metal layer 9 are open at one location. Another island-shaped metal layer (not drawn), which is electrically insulated from metallization layer 9, is applied over polysilicon layer 5 in this metal opening. It contacts polysilicon layer 5 and is used as a gate terminal.
A metallization layer 11 is likewise located on the rear side of the chip. It forms the electrical contact to highly n+-doped silicon substrate 1. Metal layer 9 forms source contact S; metal layer 11, drain contact D; and island-shaped metal layer (not shown), gate contact G. Metallization 9, respectively the island-shaped metal layer can be an aluminum alloy that is customary in silicon technology having copper and/or silicon contents or some other metal system. On the rear side, a solderable metal system 11 is applied, composed, for example, of a layer sequence of Ti, NiV and Ag.
Drain contact 11 is normally at a positive potential, while the source terminal is at ground potential. If, relative to the source contact, a high enough positive gate voltage VG is applied to the gate terminal, a thin electron inversion channel forms in body region 6 at the boundary surface to gate oxide 4. In this context, gate voltage VG must be higher than threshold voltage VTH of the transistor. The inversion channel extends from n+-doped source region 8 to n-doped epitaxial region 2. Thus, a continuous electron path is created from the source contact to the drain contact. The transistor is conductive.
Since the current flow occurs only through majority carriers, which are electrons, it can be quickly interrupted. In contrast to conventional bipolar components, the component switches very rapidly.
The doping concentration and thickness of n-doped region (epitaxial layer) 2 is determined by the blocking voltage of the transistor. The higher the blocking voltage of a MOSFET is selected, the more weakly doped and thicker region 2 must be. Since an ohmic voltage drop develops across the epitaxial region, the entire on-state resistance Rdson thereby increases. At high blocking voltages, this component dominates. Therefore, MOSFETs are generally not suited for blocking voltages over 200 V.
A vertical MOSFET, which exhibits a reduced on-state resistance, is described in U.S. Pat. No. 6,621,121 B2. This MOSFET includes a semiconductor substrate having a plurality of semiconductor mesas that are mutually separated by a plurality of strip-shaped trenches. These trenches extend mutually in parallel and, in a first direction, transversely across the substrate. Moreover, the MOSFET has a plurality of hidden, insulated source electrodes configured within the plurality of strip-shaped trenches. In addition, the MOSFET includes a plurality of insulated gate electrodes that extend mutually in parallel over the plurality of semiconductor mesas into the flat trenches which are provided in the mentioned multiplicity of hidden, insulated source electrodes. Moreover, the MOSFET has a surface source electrode on the mentioned semiconductor substrate that is electrically contacted by the plurality of hidden, insulated source electrodes and has an ohmic contact with the at least one base region in each of the plurality of semiconductor mesas.